

`include "my_matlab_pkg.sv"


module tb_tx  (
  input                             aclk   ,
  input                             areset , // not used, port required by EFI interface

  output  reg  [15:0]    slave_data_re,
  output  reg [15:0]    slave_data_im,
  output  reg           slave_tvalid,
  input              slave_tready,
  input     [15:0]   master_data_re,
  input     [15:0]   master_data_im,
  input              master_tvalid,
  output   wire           master_tready

);

import my_matlab_pkg::*;

  bit[15:0] datar[64];
  bit[15:0] datai[64];

  bit[15:0] rtl_datar[64];
  bit[15:0] rtl_datai[64];

  bit[15:0] result[1];

  reg         gen_wave_done ;
  reg  [6:0]  gen_wave_cnt  ;
 initial begin
     gen_wave_done = 'd0;
     gen_wave(datar,datai);
     for (int n=0;n<1;n++) 
     begin  
     	$display("sim data print begin ");
     	for(int i=0;i<64;i++)     
     		$display("data:  %d   %d ",datar[i],datai[i]);
     	$display("sim data print done ");
      end

      #10_000
     gen_wave_done = 'd1;

      //$finish ;
  end


  always @(posedge aclk  or posedge areset  )
  begin
	  if (areset) begin
		gen_wave_cnt <= 'd0;
	  end
	  else if (gen_wave_done && (gen_wave_cnt<='d63) )  begin
		gen_wave_cnt <= gen_wave_cnt + 'd1;
	  end
  end

  always @(posedge aclk  or posedge areset  )
  begin
	  if (areset) begin
		slave_tvalid <= 'd0;
		slave_data_re <= 'd0 ;
		slave_data_im <= 'd0 ;
	  end
	  else if (gen_wave_done && (gen_wave_cnt<='d63) )  begin
		slave_tvalid <= 'd1;
		slave_data_re <=  datar[gen_wave_cnt];
		slave_data_im <=  datai[gen_wave_cnt] ;
	  end
	  else begin
		slave_tvalid <= 'd0;
	  end
  end



  assign  master_tready = 'd1 ;



////////////////////////////////////////////////////////////////////////////////
//master_tvalid

reg   [6:0]   master_tcnt ;
  always @(posedge aclk  or posedge areset  )
  begin
	  if (areset) begin
		master_tcnt <= 'd0;
	  end
	  else if (master_tvalid && master_tready &&  ( master_tcnt <='d63) )  begin
		master_tcnt  <= master_tcnt + 'd1;
	  end
  end

  reg  master_tdone  ;
 always @(posedge aclk  or posedge areset  )
  begin
	  if (areset) begin
		master_tdone <= 'd0;
	  end
	  else if (master_tvalid && master_tready &&  ( master_tcnt =='d63) )  begin
		master_tdone  <=  'd1 ;
	  end
  end


 always @(posedge aclk  or posedge areset  )
  begin
	  if (master_tvalid && master_tready  && (master_tcnt<='d63) )  begin
		rtl_datar[master_tcnt] <=  master_data_re;
		rtl_datai[master_tcnt] <=  master_data_im;
	  end
  end



 initial begin
     wait (master_tdone) ;
     #1000
     for (int n=0;n<1;n++) 
     begin  
     	$display("check data print begin ");
	fft_checker(datar,datai,rtl_datar,rtl_datai,result);
     	$display("check data print done!!!  result is %d "  ,  result[0]);
      end


      //$finish ;
  end










endmodule



